Dynamic circuitry has long been an integral part of chip or integrated circuit design. The inherent low delay makes dynamic circuitry ideal for high speed applications, such as microprocessors, high speed logic, random access memories, etc. One popular class of dynamic circuitry is the Domino circuit.
In general, the term domino logic is used to refer to an arrangement of logic circuit stages which may, for example, be cascaded together in an integrated circuit array configuration. A signal may be inputted to a first stage where it is evaluated in order to provide an output signal to a second stage where that output signal is again evaluated to provide an output signal for propagation to and evaluation by yet another stage in the circuit. Thus a domino effect is achieved whereby signals are sequentially propagated through an array of stages or domino blocks, and each successive stage performs an evaluation of an input condition until a final output is provided at a final output stage. Domino logic circuits may be arranged so that signals can propagate through the various stages without being separately clocked at each stage.
Domino circuits consist of a domino logic block, and an NFET and PFET device pair connected to a clock signal, an output inverter (an NFET and PFET pair), and a feedback PFET device. A standard domino circuit uses logic input signals and clock signals to produce an output signal. Because of the inherent dynamic characteristic of the domino circuit, this function requires two distinct operational phases known as the precharge phase and the evaluate phase. The precharge phase sets the domino circuit to a known state during a first half cycle while the clock signal is in a low logic level. That condition typically forces the output low. The evaluate phase then permits the domino circuit to selectively switch, based on the input signals, to switch the output to a high logic level if the inputs and the logic function so determine.
The use of the Domino circuit involves some design risk and its use requires a much higher level of sophistication than a conventional simple CMOS static circuit for logic applications. The Domino circuit can fail operationally if certain conditions are not met. The primary condition is that the logic inputs to the Domino circuit must be valid during the evaluation phase of the clock. This means that the inputs must not change state during the evaluation phase. However, system electrical and other noise can cause the inputs to the Domino circuit to change state. This and other conditions are analyzed during system design to insure they are being met but the design tools are not yet fail-safe and 100% reliability cannot be guaranteed. Noise is still somewhat of an art with Domino circuitry. If an error situation is found by analysis, in a newly designed Domino circuit configuration, after release of the design to manufacturing, or by test on the first hardware, a correction or fix is necessary.
After an evaluate phase, a domino circuit cannot return to the precharge state without the precharge occurring. Therefore any false switching during the evaluate phase is non-recoverable and will cause a logical failure. Under normal operation, the domino circuit is designed to insure that false switching does not occur. However, noise on inputs and parasitic leakage may cause false switching events from which domino circuits cannot recover. Some design precautions can be taken to minimize noise and leakage problems. For example, shielding can help to minimize the coupling of events on the inputs to the domino circuit. Also, with regard to parasitic leakage through NFET devices (in the domino logic block) which may cause a loss of the precharged state, the keeper device, i.e. the feedback PFET device can be made large enough to counteract the leakage through the NFET evaluation devices inside the domino logic block. It should here be noted that the above identified false switching problems occur with dynamic domino circuits but do not occur with standard static logic circuits.
In many instances when false switching events occur in domino circuits, they are either unpredictable and due to design complexity, or happen late in a project cycle and cannot be corrected in an efficient manner. Nearly always, a complete redesign is required which will involve changes to all mask layers in order to correct the problem.
Thus there is a need to provide an improved method and apparatus for the implementation of a fix technique for failed domino circuit configurations by which noise susceptibility and false switching problems can be significantly reduced thereby increasing the reliability of domino logic circuits.